Circuit designs for integrated circuits (ICs) can be generated using a variety of techniques. In some examples, designers can write register-transfer level (RTL) code, write program-language code, create schematic representations, or a combination thereof to design a circuit for implementation in a target IC device. The target IC device can be a programmable IC, such as a field programmable gate array (FPGA), a mask-programmable IC, such as an application specific integrated circuit (ASIC), or the like. In the design flow, a designer creates a description of the circuit design, which is then processed through one or more steps that transform the description into a physical implementation of the circuit design for a target IC device.
Programmable ICs, such as FPGAs, typically include programmable logic that can be configured by loading configuration data into configuration memory cells. In FPGAs, for example, each configuration memory cell comprises a static random access memory (RAM) cell. A configuration memory cell can exhibit an unintentional change in state when the programmable IC is subjected to radiation, such as cosmic rays, bombardment by neutrons or alpha particles, or the like. For example, a stored logic high value can be inadvertently changed to a logic low value and vice versa. Such “single-event upsets” can alter the functionality of a circuit configured in the programmable IC, which can cause the circuit to fail. The rate of failure of a circuit due to single-event upsets is referred to as the single-event failure rate or “SER.”